1. Field of the Invention
The present invention relates to a discharging circuit and, more particularly, to a data bus discharging circuit capable of enabling high-speed operation of microprocessors and microcomputers.
2. Description of the Prior Art
It is a general practice so far to initialize all the bit lines of the internal data bus of a MOS circuit device, such as a MOS microprocessor or a MOS microcomputer, at the level of the power source potential V.sub.DD (logic "1") immediately before starting data transfer, for the high-speed transfer of the data accumulated in the internal register of the MOS circuit device to the data bus.
An improved data bus precharging circuit for the high-speed initialization of a data bus is disclosed, for example, in Japanese Unexamined Patent Publication No. 58-186827 by the inventors of the present invention.
However, in transferring the data of a logic "0" stored in the internal register to the bit lines of the data bus set at the level of the power source potential, reducing the potential of the bit lines to the ground potential (logic "0") requires a considerably long time, for example, 50 to 60 ns, due to the parasitic capacitance of the bit lines.
Accordingly, it has been extremely difficult to operate a microprocessor IC at a high speed with clock signals of 15 MHz or above.
The enhancement of the output driving capability of thirty to forty registers may make it possible to solve such a problem; however, such means requires microprocessor IC chips having a large area, which disadvantageously increases the manufacturing cost.